1. Field of the Invention
The present invention relates to semiconductor design, and more specifically to optimizing semiconductor repeater design.
2. Description of the Related Art
A central processing unit (CPU) typically includes many components such as a processor core, cache memory, and registers. Further, within the components are logic elements such as NOR, NAND and inverters, which are manufactured from circuit elements such as transistors and conductive wires. Designing the CPU involves resolving many problems such as accounting for multiple operating frequencies between the components, jitter, and attenuation. For example, if a processor core operates at a higher frequency than a register outside the processor core, resulting in clock timing differences between the components, then a phase-locked loop (PLL) or delay-locked loop (DILL) circuit can resolve the differences. DLL circuits can also resolve jitter, which is noise propagated along a signal by other circuit elements, such as a power supply. Similarly, other circuit elements can resolve attenuation, which is the reduction of a signal during transmission.
FIG. 1 is a diagram illustrating a central processing unit having multiple cores. A CPU 100 can include multiple cores 110 and modules 130 connected together via connectors 120. The connector 120 is a conductive interconnect metal line (e.g. copper or the like) and module 130 can be memory or an I/O controller. Cores 110 can also have a driver 150, a transceiver 155, and a receiver 160. The driver 150 can drive a signal to the transceiver 155, which receives the signal and transmits to the receiver 160. Connectors 120 can also have multiple repeater locations 140. Further, a core solution 170 can include two repeater locations 140 in the core 110.
During the design phase, an optimal repeater solution includes multiple repeater locations 140 that propagate signals along the connectors 120 with minimal problems. However, by designing the optimal repeater solution, each component will have different repeater solutions. For example, as shown in FIG. 1, one core 110 has the core solution 170 while another core 110 does not. In a design that includes more than two cores, the problem of different repeater solutions increase development costs because each core 110 can have different core solutions 170.
Another problem from the design illustrated in FIG. 1 is the placement of multiple repeater solutions 140 between the cores 110 and modules 130. When the CPU 100 has one core 110 with the core solution 170 and another core 110 without the core solution 170, the CPU 100 includes many repeater locations 140 outside the cores 110. These repeater locations 140 take up valuable space on the CPU 100 and further add circuit elements that increase the operating temperature of the CPU 100.
Accordingly, what is needed is a method and apparatus for inserting repeaters in a CPU 100 to solve problems such as resolving multiple clock frequencies and attenuation, while reducing design and manufacturing costs.